With ever increasing demands to reduce both the size of devices and their power consumption, it is becoming increasingly challenging to design robust semiconductor memories such as SRAM. Each storage cell in an SRAM comprises a feedback loop for holding a data value. In order to write to the feedback loop and store a new value, the input must have a high enough voltage level to be able to switch the state stored by the feedback loop if required, while reading from the feedback loop should be performed without disturbing the values stored in any of the feedback loops.
As dimensions scale down the variations in device properties due to random dopant fluctuations, line edge roughness etc. increase drastically.
Thus, designing a robust SRAM where cells can be read (without read disturb) and written to across all operational voltage ranges turns out to be very difficult. Reducing the voltage at which the SRAM cells can be read and written to successfully is not easy and in particular as the voltage scales down it becomes increasingly difficult to write to the cells.
One proposed way of addressing the write problem is disclosed in “Low power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-IV Operation” by Iijima et al. Journal of Computers, vol 3, No 5 May 2008. In this article an active body-biasing controlled boost transistor generates a boost to the word line voltage thereby facilitating writes by capacitive coupling only when accessed. A drawback of this scheme is that there is a significant area overhead resulting from having one extra transistor per word line and also this transistor adds an additional delay to the turning off of the pass gate. The pass gate allows access to the storage cell, and this extra delay results in some charge leakage and therefore decreases the efficiency of the scheme.
In addition to the above drawbacks, such schemes as this only address the write-ability problems and not the problems associated with read disturb where an increased voltage on the word line makes it more likely that cells may be unintentionally corrupted.
It would be desirable to be able to reduce both read and write failures particularly during low voltage operation of a semiconductor memory.